Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

Sub-threshold SRAM Sense Amplifier Compensation Using Auto-zeroing Circuitry

Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bit-line differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduc...

A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-Threshold Sense Amplifiers

Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times and causes increased power consumption. The effect aggravated in the sub-threshold region. In this paper, we propose a circuit that reduce...

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing

A novel area-efficient dual replica-bitline delay technique is proposed in this brief to improve process-variation-tolerance of low voltage SRAM application. This strategy suppresses the timing variation by adding one another replica-bitline and introducing novel replica cell which has the same size as conventional. Simulation results in TSMC 65nm LP technology show that more than 32.3% timing ...

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]

A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM

A novel ultra high speed, compact and least sensitive to process variation, hybrid sense amplifier is designed for ultra low power SRAM. Precisely sized current mode circuit (CMC) is designed to provide differential current from bit-lines. We eliminate the global sensing stage to save silicon area and sized the output buffers to achieve full logic swing at the output of proposed sense amplifier...